Every design is different, so why is every embedded processor the same?

All too often the strength and speed of security are at the mercy of one another. SecureRF’s WalnutDSATM offers an alternative, resisting all currently known quantum attacks while decreasing verification time. Using WalnutDSA, Codasip’s team developed a RISC-V compliant processor and implemented the digital signature protocol in less then one week. 

This presentation covers the following topics and more:

  • How SecureRF produces quantum-resistant security  for low resource devices using group
     theoretic cryptography.
  • Why – and how – to implement RISC-V for ASIP.RISC_V_Presentation.png
  • How the team reduced the math required to support the DSA from 24 instructions to one custom instruction.
  • Benchmarking results including verification time, code size and FPGA resources used vs ECC.

This material was presented by Drake Smith and Derek Atkins of SecureRF (Dan Ganousis of Codasip was unable to attend), during the RISC-V Workshop hosted by MIT, July 12-13, 2016.

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